Semiconductor devices may use strained SiGe to reduce short channel effects to improve the device performance. However, SiGe structures are susceptible to strain relaxation causing wafer deformation during thermal annealing. When wafer deformation occurs it leads to stress induced misalignment errors during subsequent lithography processes which ultimately results in substantial yield losses in fabrication of state-of-the-art complementary metal-oxide-semiconductor (“CMOS”) devices.
In addition, as devices are increasingly scaled down in size the contact-to-gate overlay requirements become more stringent. When the devices are scaled down the critical layers frequently fail to meet alignment targets due to the wafer deformation occurring during laser annealing, for example, laser spike annealing (“LSA”). The problem of the critical layers failing to properly align is aggravated by the fact that in-line metrology to quantify LSA-induced warpage is not readily available and becomes apparent only when the wafer fails for overlay at the lithography (“LIT”) step. By the time the wafer reaches the LIT step it is too late to correct the root cause of the misalignment.
This process is problematic for the resultant semiconductor device because the wafer deformation and ultimate layer misalignment may cause the deformed wafer to be unusable. Further, currently used fabrication techniques fail to provide optimization to reduce misalignment errors at the critical layers.